MRIGANKO S. DUTTA
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ABOUT
RESEARCH & THESIS
HONOURS
PROJECTS
ACADEMICS
EXPERIENCE & LEADERSHIP
CV

MRIGANKO SHEKHAR DUTTA

Master of Science by Research
Computer Science and Engineering, IIT Bombay
Research Groups: CASPER and Trust Lab
Curriculum Vitae Email GitHub LinkedIn
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Hi! I'm available for internships and full time roles.

ABOUT

I'm a final-year postgraduate student at the Department of Computer Science and Engineering, IIT Bombay, pursuing my MS by Research under the guidance of Prof. Biswabandan Panda. My research interests lie in Computer Architecture, specifically microarchitectural performance and security. I'm currently working on research topics in frontend microarchitecture and cache management.

Outside of academics, I enjoy resistance training, cooking, and macro photography—capturing the unnoticed yet always present through my lens.

RESEARCH & THESIS

My research focuses on computer architecture, microarchitectural performance, and hardware security, particularly:

Master's Thesis & Research Projects

Designing a High-Performance Cache Management Policy for Datacenter Processors

Aug ’25 – Present
M.S. Thesis | Guide: Prof. Biswabandan Panda
  • Observed that state-of-the-art instruction-aware L2 replacement policies, which are targeted towards minimizing instruction fetch stalls by prioritizing instruction lines, inadvertently increase data load misses by 19.84%.
  • Developed a novel L2 cache replacement policy that addresses both frontend and backend CPU pipeline stalls by identifying and prioritizing critical (costly) cache misses at L2, based on program execution behavior.
  • Achieved a speedup of 14.90% over the baseline SRRIP replacement policy, requiring 60% lesser storage overhead than the state-of-the-art replacement policy ICARUS (ASPLOS ’26) which achieves a speedup of 12.98%.

Performance Evaluation of Instruction-Aware L2 Cache Replacement Policies for Datacenter CPUs

Jan ’25 – Jul ’25
Seminar and R&D II Project | Guide: Prof. Biswabandan Panda
  • Conducted a literature survey to understand the intricacies of the frontend design of datacenter CPU pipelines.
  • Analyzed the performance of state-of-the-art instruction-aware cache replacement policies on the gem5 simulator in full-system mode across 12 datacenter workloads.
  • Identified pitfalls in the current instruction-aware replacement policies and proposed possible solutions.

Securing the Instruction Cache from Transient Execution Attacks

Aug ’24 – Dec ’24
R&D I Project | Guide: Prof. Biswabandan Panda
  • Conducted a literature survey to understand transient execution attacks and their mitigations.
  • Extended the GhostMinion cache (MICRO ’21) idea to the L1 instruction cache on the ChampSim simulator mitigating frontend pipeline misprediction leaks.

HONOURS & ACHIEVEMENTS

Smt. Chander Mohini Kapoor and Jeewan Kapoor Award 2026

Honored for demonstrating top-tier research and technical project performance among Master’s candidates at IIT Bombay.

Perfect AA Grade in Master’s Research Modules

Achieved a perfect 10/10 grade in both Master’s Research (R&D I & II) and Seminar modules at IIT Bombay.

Silver Medalist (2nd Rank out of 357 graduates)

Awarded Silver Medal for ranking 2nd out of 357 graduates in B.Tech, Computer Science and Engineering, Techno India University, Kolkata.

KEY PROJECTS

Microarchitecture Conscious Optimization for Matrix and Convolution Operations

Aug ’24 – Nov ’24
CS683: Advanced Computer Architecture | Instructor: Prof. Biswabandan Panda
C++ SIMD Vectorization Cache Tiling Software Prefetching
  • Optimized matrix transpose operations on a real system using microarchitecture-conscious programming techniques like cache tiling, SIMD vectorization, and software prefetching to maximize cache utilization.
  • Achieved a 6x reduction in L1 data cache misses by eliminating non-contiguous memory access stalls, resulting in an average speedup of 90.32% (up to 4.5x) over naive matrix transpose baseline.
  • Extended these optimizations to 2D-convolution operations achieving 4x – 5x speedup by optimizing kernel matrix multiplication over naive 2D-convolution baseline.

Performance Optimization Using Data Prefetching Techniques

Aug ’24 – Nov ’24
CS683: Advanced Computer Architecture | Instructor: Prof. Biswabandan Panda
ChampSim C++ Hardware Prefetching Adaptive Throttling
  • Achieved a speedup of 1.41x – 3.82x over no prefetching by implementing IP stride, Stream, and Stream+Stride prefetchers coupled with adaptive prefetch throttling, leading to an overall performance boost.
  • Reported a 42.73% reduction in L1 data misses and ~80% prefetch accuracy across different prefetch strides and distances.

Scalable Distributed Key-Value Store Server

Aug ’24 – Nov ’24
CS744: Design and Engineering of Computing Systems | Instructor: Prof. Purushottam Kulkarni
C++ Distributed Systems Dynamic Sharding TCP/IP Sockets LRU Cache
  • Architected a distributed, multi-threaded Key-Value store in C++ supporting dynamic data sharding across multiple nodes via hashing and TCP/IP sockets.
  • Engineered a thread-safe LRU cache, coupled with a peer-to-peer cache invalidation protocol over TCP to maintain strict data consistency and eliminate stale reads across distributed nodes.

Flash Attention Optimization of LLM Training and Inference

Jan ’26 – Jul ’26
CS794: Systems for Machine Learning | Instructor: Prof. Mythili Vutukuru
CUDA GPU Systems FlashAttention LLM Acceleration
  • Implemented a forward-pass FlashAttention (arXiv ’22) CUDA kernel, eliminating O(N²) HBM memory accesses by tiling Query, Key, and Value blocks directly into GPU scratchpad memory.
  • Implemented an online softmax algorithm within the kernel loop, dynamically updating running statistics to compute tiled attention without storing intermediate matrices in global memory.

Linux Kernel-Level Process Monitoring and Address Translation via LKM

Jan ’25 – Jul ’25
Self Project
C++ / C Linux Kernel Modules ioctl VirtualBox
  • Implemented custom Linux Kernel Modules (LKM) integrated with VirtualBox VMs to monitor process-related information (PID, child processes, process states, and size of mapped virtual addresses).
  • Built an ioctl device driver that translates virtual to physical addresses and updates memory content using Linux’s task_struct, mm_struct, vm_area_struct, and maple_tree structures.

BeeHive - A Web-based Peer-to-Peer File Sharing Platform

Aug ’25 – Nov ’25
Self Project
C++ WebSockets epoll P2P Mesh JavaScript
  • Architected a C++ P2P distribution system that offloaded redundant 1-to-many server downloads to a browser-based mesh, drastically reducing server load during mass distribution.
  • Engineered a custom WebSocket signaling tracker in C++ using Linux epoll I/O multiplexing and a worker pool, utilizing reader-writer locks (std::shared_mutex) for thread-safe peer state management under high concurrency.

Technical Skills

Programming & Scripting

C C++ Python CUDA Bash Sed Awk

Simulation Tools

gem5 ChampSim Cacti

Performance & Profiling

Intel VTune perf

Development & Systems

Git Tmux GDB Linux Kernel (LKM) VirtualBox Zeek

ACADEMICS

Education Journey

Master of Science by Research in Computer Science and Engineering

2024 – Present
Indian Institute of Technology Bombay, Mumbai CPI: 8.69

Bachelor of Technology in Computer Science and Engineering

2020 – 2024
Techno India University, Kolkata CPI: 9.28

AISSCE (Class XII), CBSE

2018 – 2020
South Point High School, Kolkata 81.60%

AISSE (Class X), CBSE

2018
South Point High School, Kolkata 92.20%

Courses Taken

EXPERIENCE & LEADERSHIP

System Administrator

Sept ’25 – Present
Trust Lab, IIT Bombay | Apprenticeship | Mumbai
  • Administered Linux servers and virtual environments by implementing strict access controls and advising on infrastructure upgrades to ensure infrastructure stability for 50+ researchers.
  • Deployed a 24/7 network logging pipeline using Zeek for a public-facing server, securely routing data to an internal log sink and eliminating the need for paid enterprise solutions.

Teaching Assistant | CS683: Advanced Computer Architecture

Jul ’25 – Present
Department of Computer Science and Engineering, IIT Bombay
  • Designed assignments, conducted vivas, and provided academic support to more than 400+ students.

Teaching Assistant | INAE Faculty Development Programme

Jul ’26 – Jul ’26
Indian National Academy of Engineering (INAE) & Infosys Foundation
  • Guided 50+ faculty from engineering institutions across India in computer architecture for the INAE faculty development programme, backed by the Infosys Foundation.